swe[zeke]den
New member
library IEEE;
use IEEE.std_logic_1164.all;
entity count21 is
port (clock: in std_logic;
ut: out std_logic_vector (20 downto 0));
end count 21;
architecture beteende of count21 is
attribute state_vector of beteende;
architecture is 'state';
attribute state_encoding of beteende;
architecture is 'binary';
subtype states is integer range 0 to 20;
signal state, nextstate: states;
begin
process (state)
begin
case state is
when 0 to 19 => nextstate nextstate